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    • 专利摘要:
    An optoelectronic device (50) comprising semiconductor elements (20), each semiconductor element resting on a carrier (16) through an opening (54) formed in a portion (52), at least a first part is insulating and at least partially covering the support, the height (H) of the opening being greater than or equal to 100 nm and less than or equal to 3000 nm and the ratio between the height (H) and the smallest diameter of the opening (L) being greater than or equal to 0.5 and less than or equal to 10.
    公开号:FR3016082A1
    申请号:FR1363700
    申请日:2013-12-30
    公开日:2015-07-03
    发明作者:Erwan Dornel；Benoit Amstatt；Philippe Gilet
    申请人:Aledia；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present invention relates generally to optoelectronic devices based on semiconductor materials and their manufacturing processes. BACKGROUND OF THE INVENTION The present invention more particularly relates to optoelectronic devices comprising semiconductor elements of micrometric or nanometric size, in particular microwires, semiconductor nanowires or structures of pyramidal shape.
    [0002] BACKGROUND OF THE PRIOR ART Semiconductor elements of micrometric or nanometric size, in particular microfilts, nanowires or pyramidal-shaped structures comprising a semiconductor material comprising in particular predominantly a Group III element and a Group V element (for example nitride gallium GaN), hereinafter called compound III-V, allow the manufacture of semiconductor devices such as optoelectronic devices. By optoelectronic devices are meant devices adapted to perform the conversion of an electrical signal into an electromagnetic radiation or vice versa, and especially devices dedicated to the detection, measurement or emission of electromagnetic radiation or devices dedicated to photovoltaic applications. Processes for manufacturing micron-sized or nano-sized semiconductor elements comprising a III-V compound should enable fabrication of these semiconductor elements with precise and uniform control of the geometry, position, and crystallographic properties of each semiconductor element.
    [0003] The manufacture of an optoelectronic device comprising semiconductor elements of nanometric or micrometric size generally comprises the formation of seeds on a layer made of a material that promotes the formation of nuclei of the compound III-V, called the nucleation layer, the growth of the semiconductor elements. from the seeds and the formation of an active layer on each semiconductor element. To control the growth sites of the semiconductor elements, the nucleation layer is, for example, covered with an insulating layer in which are made openings exposing portions of the nucleation layer. It is desirable that only one seed be formed on the nucleation layer in each opening. However, several germs can form in the same opening. This can lead to the growth of several semiconductor elements from the same opening. A poor control of the growth of these semiconductor elements is then obtained, especially as regards the height and the orientation of each semiconductor element. This can lead to a degradation of the operation of the optoelectronic device.
    [0004] SUMMARY Thus, an object of an embodiment is to overcome at least in part the disadvantages of optoelectronic device manufacturing processes comprising semiconductor elements of micrometric or nanometric size, in particular microwires, semiconductor nanowires B13042 or pyramidal structures, described above and their manufacturing processes. Another object of an embodiment is to obtain the growth of a single semiconductor element from each opening of the insulating layer covering the seed layer. Another object of an embodiment is to control the orientation of the growing semiconductor element since each opening of the insulating layer overlying the seed layer. Another object of an embodiment of the present invention is that the position, geometry and crystallographic properties of each III-V compound semiconductor element can be accurately and uniformly controlled. Another object of an embodiment is that optoelectronic devices with nanoscale or micron sized semiconductor elements can be manufactured on an industrial scale and at low cost. Thus, an embodiment provides an optoelectronic device comprising semiconductor elements, each semiconductor element resting on a support through an opening formed in a portion at least partially covering the support and of which at least a first portion is insulating, the aperture height being greater than or equal to 100 nia and less than or equal to 3000 nia and the ratio between the height and the smallest diameter of the opening being greater than or equal to 0.5 and less than or equal to 10. According to one embodiment, the semiconductor elements are nanowires, microwires and / or pyramidal structures of nanometric or micrometric size. According to one embodiment, the height is greater than or equal to 200 nia. According to one embodiment, the ratio is greater than or equal to 1.
    [0005] According to one embodiment, the average diameter of the opening is constant over the entire height of the portion. According to one embodiment, the average diameter of the aperture decreases continuously from the apex of the aperture to the base of the aperture. According to one embodiment, the opening comprises successively from the base of the opening a first portion and a second portion, the average diameter of the first portion being constant over the entire height of the first portion and the average diameter of the second part being constant over the entire height of the second part and different from the average diameter of the first part. According to one embodiment, the average diameter of the first portion is strictly less than the average diameter of the second portion. According to one embodiment, the average diameter of the first part is strictly greater than the average diameter of the second part. According to one embodiment, the first portion of the portion comprises at least one of the materials of silicon oxides, silicon nitrides and aluminum oxides. According to one embodiment, at least a second portion of the portion comprises at least one non-electrically insulating material. According to one embodiment, the second portion of the portion comprises at least one of the materials selected from the group consisting of AIN, Ti, TiN, Ta, TaN, Hf, HfN, WNW, Mo. According to one embodiment each semiconductor element is predominantly a III-V compound. According to one embodiment, each semiconductor element mainly comprises gallium nitride. One embodiment provides a method of manufacturing an optoelectronic device comprising the following steps: B13042 forming, on a support, a portion at least partially covering the support and at least a first portion is insulating; forming an opening through the portion, the height of the opening being greater than or equal to 100 nm and less than or equal to 3000 nm and the ratio between the height and the average diameter of the opening at the top of the portion being greater or equal to 0.5 and less than or equal to 10; and growing in each aperture a semiconductor element resting on the support. According to one embodiment, the height of the portion is greater than or equal to 100 nm and less than or equal to 1000 rira. According to one embodiment, the formation of the portion comprises the following steps: depositing a first insulating layer comprising a first insulating material; depositing a second insulating layer comprising a second insulating material different from the first insulating material; forming a first portion of the opening in the first insulating layer; forming a second portion of the opening in the second portion of the insulating layer, the average diameter of the first portion being different from the average diameter of the second portion; and growing in each first and second portion of the aperture a semiconductor element resting on the support. According to one embodiment, the formation of the portion comprises the following steps: deposition of a first insulating layer (96) comprising a first insulating material; forming a first portion of the aperture in the first insulating layer; Depositing a second insulating layer comprising a second insulating material different from the first insulating material; forming a second portion of the opening in the second portion of the insulating layer, the average diameter of the first portion being different from the average diameter of the second portion; and growing in each first and second portion of the aperture a semiconductor element resting on the support. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying drawings in which: the schematic, microwires or schematic, of a method shown in Figure 1 is a sectional view, partial and an example of a nanowire optoelectronic device; FIGS. 2A to 2C are partial sections and structures obtained at successive manufacturing steps FIG. 1; Figures 3 to 5 are partial sectional views of the optoelectronic device and schematic of embodiments of optoelectronic devices with microwires or nanowires; Figures 6 and 7 are partial sectional and schematic views of embodiments of optoelectronic devices respectively truncated pyramids and pyramids; Figures u. at 8C are partial and schematic sections of structures obtained at successive steps of an embodiment of a method of manufacturing the optoelectronic device shown in FIG. 3; Fig. 9 is a partial and schematic sectional view of the structure obtained at a step of an embodiment of a method of manufacturing the optoelectronic device shown in Fig. 7; FIGS. 10 and 11 are sectional, partial and schematic views of other embodiments of optoelectronic devices with microwires or nanowires; Figs. 12A to 12C and Figs. 13A and 13B are partial and schematic sections of structures obtained at successive steps of embodiments of a method of manufacturing the optoelectronic device shown in Fig. 11; FIG. 14 is a partial schematic sectional view of another embodiment of an optoelectronic device with microwires or nanowires; FIGS. 15A to 15C are partial and schematic sections of structures obtained at successive steps of an embodiment of a method of manufacturing the optoelectronic device shown in FIG. 14; and FIGS. 16A to 16F are partial and schematic sections of structures obtained at successive steps of another embodiment of a method of manufacturing the optoelectronic device shown in FIG. 11. Detailed Description For the sake of clarity, FIGS. The same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the electronic circuits, the various figures are not drawn to scale. In addition, only the elements useful for understanding the present description have been shown and are described. In particular, the polarization means of the optoelectronic device are well known and are not described. In the rest of the description, unless otherwise indicated, the terms "substantially", "about" and "of the order of" mean "to within 10%". In addition, "compound composed mainly of a material" or "compound based on a material" is understood to mean that a compound comprises a proportion greater than or equal to 95% of said material, this proportion being preferentially greater than 99%. The present disclosure relates to optoelectronic devices comprising semiconductor elements in the form of microwires, nanowires or pyramids. The term "microfil" or "nanowire" refers to a three-dimensional structure of elongated shape in a preferred direction of which at least two dimensions, called minor dimensions, are between 5 nia and 2.5 pin, preferably between 50 nia and 2, 5 pin, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the largest of the minor dimensions. In some embodiments, the minor dimensions may be less than or equal to about 1 pin, preferably between 100 nia and 1 pin, more preferably between 100 nia and 800 nia. In some embodiments, the height of each microfil or nanowire may be greater than or equal to 500 nia, preferably between 1 gm and 50 pin. In the remainder of the description, the term "wire" is used to mean "microfil or nanowire". Preferably, the mean line of the wire which passes through the barycenters of the straight sections, in planes perpendicular to the preferred direction of the wire, is substantially rectilinear and is hereinafter referred to as the "axis" of the wire. In the rest of the description, the term "pyramid" or "truncated pyramid" denotes a three-dimensional structure of which part is of pyramidal or elongated conical shape. This pyramidal structure can be truncated, that is to say that the top of the cone is absent, leaving room for a plateau. The base of the pyramid is inscribed in a polygon whose side dimension is 100 nia to 10 pin, preferably between 1 and 3 pin. The polygon forming the base of the pyramid may be a hexagon. The height of the pyramid between the base of the pyramid and the summit or the summit plateau varies from 100 nm to 20 pin, preferably between 1 gm and 10 pin. In the remainder of the description, embodiments will be described in the case of an optoelectronic device with light-emitting diodes. However, it is clear that these embodiments may relate to other applications, including devices dedicated to the detection or measurement of electromagnetic radiation or devices dedicated to photovoltaic applications. Figure 1 is a partial sectional and schematic sectional view of an example of an optoelectronic device 5 with light emitting diodes. FIG. 1 shows a structure comprising, from bottom to top: a first electrode 8; a semiconductor substrate 10 comprising a lower face 11 and an upper face 12, the lower face 11 being covered with the first electrode 8 and the upper face 12 preferably being flat at least at the level of the light-emitting diodes; a seed layer 16 of a conductive material promoting son growth and disposed on the face 12; an insulating layer 18 covering the seed layer 12 and including apertures 19 exposing portions of the seed layer 16; wires 20 (three wires being shown), each wire 20 being in contact with the seed layer 16 through one of the openings 19; An insulating layer 26 extending on the lateral flanks of a lower portion of each wire 20; a shell 28 comprising a stack of semiconductor layers covering an upper portion of each wire 20; B13042 a layer 30 forming a second electrode covering each shell 28 and extending, further, on the insulating layer 26; and an encapsulation layer 34 covering the whole of the structure and in particular the electrode 30. The assembly formed by each wire 20 and the associated shell 28 constitutes a LED light emitting diode. The shell 28 includes in particular an active layer which is the layer from which the majority of the electromagnetic radiation 10 supplied by the LED is emitted. The LEDs can be connected in parallel and form a set of light-emitting diodes. The assembly can include from a few LEDs to a thousand light emitting diodes. FIGS. 2A to 2C illustrate the initial steps of an exemplary method of manufacturing the optoelectronic device shown in FIG. 1. FIG. 2A shows the structure obtained after the following steps: formation on the face 12 of the substrate 10 of the germination layer 16, for example by epitaxy; forming the insulating layer 18 on the seed layer 16; forming the openings 19 in the insulating layer 18, a single opening 19 being shown in Figures 2A-2C. The insulating layer 18 may be of a dielectric material, for example silicon oxide (SiO 2). By way of example, the thickness of the insulating layer 18 is between 5 nm and 100 nm, for example equal to approximately 30 nm. The section of each opening 19 corresponds substantially to the desired section of the wire 20. Preferably, the diameter of the wire 20 is between 100 nm and 1 pin, preferably between 300 nm and 800 nm.
    [0006] FIG. 2B shows the structure obtained after the growth of seeds in the openings 19, for example by metalorganic chemical vapor deposition (MOCVD). The inventors have demonstrated that several seeds can be formed in the same aperture 19, three seeds 36, 37, 38 being represented by way of example in FIG. 2B. Figure 2C shows the structure obtained after son growth. As shown in this figure, when several seeds 36, 37, 38 are initially present in the same opening 19, several son 39, 40 can grow from this opening 19 with different growth axes. FIG. 3 is a partial, schematic sectional view of an embodiment of an optoelectronic device 50 with light-emitting diodes whose semiconductor elements correspond to nanowires or microwires. The optoelectronic device 50 comprises the same elements as the optoelectronic device 5 shown in FIG. 1, with the difference that the insulating layer 18 is replaced by a layer 52 comprising openings 54 in each of which one of the wires 20 grows. With its associated apertures 54 may have different characteristics of the layer 18 as detailed below. In the remainder of the description, the apex of the opening 54 is called the end of the opening 54 furthest from the nucleation layer 16 and the base of the opening is the end of the aperture 54 closest to nucleation layer 16. FIG. 4 is a partial schematic sectional view of another embodiment of an optoelectronic light-emitting diode device 60. The optoelectronic device 60 comprises the same elements as the optoelectronic device 50 shown in FIG. 3, except that the seed layer 16 is replaced by seed pads 62, also called seed islands. Each wire 20 grows on one of the seed pads 62. FIG. 5 is a partial, schematic sectional view of another embodiment of an optoelectronic device 70 with light-emitting diodes. The optoelectronic device 70 comprises the same elements as the optoelectronic device 60 shown in FIG. 4 with the difference that the insulating layer 52 is divided into insulating blocks 71, each insulating block 71 covering one of the seed pads 62 and comprising the opening 54. The optoelectronic device 70 further comprises a dielectric region 72 which extends in the substrate 10 from the face 12 between the seed pads 62 and, optionally, a dielectric region 73 on the lateral flanks of each seed portion 62, the wires not growing on these dielectric regions 72, 73. Figure 6 is a partial sectional and schematic sectional view of another embodiment of an optoelectronic device 75 with light-emitting diodes. The optoelectronic device 75 comprises the same elements as the optoelectronic difference device that the opening portion 54 is replaced pyramid 76 rests on the underlying aperture 54. FIG. 7 is shown in FIG. 3 at the end of each wire 20 outside by a pyramid 76. The base of the layer 52 and is wider than a sectional, partial and schematic view of another embodiment an optoelectronic device 77 with light-emitting diodes. The optoelectronic device 77 comprises the same elements as the optoelectronic device 75 shown in FIG. 6 with the exception that each pyramid 76 is replaced by a truncated pyramid 78. In the following description, unless otherwise indicated, the term pyramid designates indifferently a complete pyramid 76 as shown in FIG. 6 or a truncated pyramid 78 as shown in FIG.
    [0007] In the case of wires 20, the diameter of the wire is substantially the same as the diameter of the corresponding aperture 54. In the case of pyramids 76, 78, there is an enlargement of the semiconductor structure right out of the opening 54. The straight section of the openings 54 may have different shapes, such as, for example, an oval, circular or polygonal shape. , in particular triangular, rectangular, square or hexagonal. When the "diameter" or "average diameter" is mentioned here in a straight section of an opening or wire, it is a quantity associated with the surface of the structure referred to in this section. , corresponding, for example, to the diameter of the disc having the same area as the cross section of the opening or wire. This same principle of equivalent diameter can be applied to the pyramidal structures especially for the base of the pyramid. H is the height of the opening 54, i.e., the thickness of the layer 52, and L the diameter of the opening 54. Preferably, the diameter L of the opening 54 is substantially constant for the entire height H. By way of example, the height H of each opening 54 is between 100 nia and 1500 nia, preferably between 200 nia and 1000 nia, even more preferably between 300 nm and 1000 nia. By way of example, the diameter L of each opening 54 is between 200 nia and 1 pin, preferably between 300 nia and 800 nia. The ratio F between the height H and the diameter L is between 0.5 and 15, preferably between 1 and 10, in particular about 1.5. The inventors have shown that when the openings 54 had the dimensions H, L and F indicated above, the growth of a single wire 20 per opening 54 was observed. The substrate 10 can correspond to a monoblock structure or correspond to a layer covering a support 35 made of another material. The substrate 10 is preferably a semiconductor substrate, for example a silicon, germanium, silicon carbide, III-V compound, such as GaN or GaAs, or a ZnO substrate. Preferably, the substrate 10 is a monocrystalline silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing processes implemented in microelectronics. The substrate 10 may correspond to a multilayer structure of silicon on insulator type, also called SOI (acronym for Silicon On Insulator).
    [0008] The substrate 10 may be heavily doped, weakly doped or undoped. In the case where the substrate is heavily doped, the semiconductor substrate 10 may be doped so as to lower the electrical resistivity to a resistivity close to that of the metals, preferably less than a few mohm.cm.
    [0009] The substrate 10 is, for example, a heavily doped substrate with a dopant concentration of between 5 * 1016 atoms / cm3 and 2 * 1020 atoms / cm3. In the case where the substrate is weakly doped, for example with a dopant concentration less than or equal to 5 * 1016 atoms / cm 3, preferably substantially equal to 10 15 atoms / cm 3, a doped region of the first type of conductivity or a second type of conductivity, opposed to the first type, more strongly doped than the substrate may be provided which extends in the substrate 10 from the face 12 under the seed layer 16. In the case of a silicon substrate 10, Examples of P type dopants are boron (B) or indium (In) and examples of N type dopants are phosphorus (P), arsenic (As), or antimony (Sb). The face 12 of the silicon substrate 10 may be a face (100).
    [0010] The seed layer 16 or the seed pads 62 are made of a material that promotes the growth of the yarns 20 or the pyramids 76, 78. By way of example, the material making up the seed layer 16 or the seed pads 62 can be a transition metal nitride, carbide or boride of column IV, v or vr of the periodic table of elements or a combination thereof. For example, the seed layer 16 may be aluminum nitride (A.1N), boron (B), boron nitride (BN), titanium (Ti), titanium nitride (TiN) ), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride (HfN), niobium (Nb), niobium nitride (NbN), zirconium (Zr) of zirconium borate (ZrB 2), zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), magnesium nitride in the form MgxNy, where x is about equal to 3 and y is approximately equal to 2, for example magnesium nitride according to the form Mg3N2 or gallium and magnesium nitride (MgGaN), tungsten (W), tungsten nitride (WN) or a combination of those -this. The seed layer 16 may be doped with the same type of conductivity as the substrate 10. The insulating layer 52 may be of a dielectric material, for example silicon oxide (SiO 2), silicon nitride (SixNy, where x is about equal to 3 and y is approximately equal to 4, for example Si3N4), to silicon oxynitride (in particular of general formula SiOxNy, for example Si2ON2), to aluminum oxide (A.1203), to hafnium oxide (Hf02) or diamond. The insulating layer 52 may have a monolayer structure or correspond to a stack of two layers or more than two layers. When the insulating layer 52 corresponds to a stack of at least two layers, the upper layer of the stack is of insulating type, for example a dielectric material. The lower layer or layers of the stack between the seed layer 16 and the insulating upper layer may be of dielectric material. As a variant, the lower layer or layers may be made of a semiconductor or metal material, for example aluminum nitride (A.1N), boron (B), boron nitride (BN) or titanium (Ti). ), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), hafnium (Hf), hafnium nitride B13042 16 (HfN), niobium (Nb), nitride of niobium (NbN), zirconium (Zr), zirconium borate (ZrB2), zirconium nitride (ZrN), silicon carbide (SiC), nitride and tantalum carbide (TaCN), tungsten (W) or tungsten nitride (WN). This list is not exhaustive. It is also possible to form a "sandwich" of conductive and insulating materials. In particular, the layer 52 may comprise a stack of several layers, some of which may be used as etch stop layers during etching operations. In particular, the seed layer 16 may be covered with a protective layer having a height of between 30 nia and 50 nia. The wires 20 are at least partly formed from at least one semiconductor material. The semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound or a combination of at least two of these compounds. The wires 20 or pyramids 76, 78 may be at least partially formed from semiconductor materials predominantly comprising a III-V compound, for example a III-N compound. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements may also be used, for example, phosphorus or arsenic. In general, the elements in compound III-V can be combined with different mole fractions. The wires 20 may be, at least in part, formed from semiconductor materials predominantly comprising a II-VI compound. Examples of Group II elements include Group IIA elements, including beryllium (Be) and magnesium (Mg) and Group IIB elements, including zinc (Zn), cadmium (Cd) and mercury ( Hg). Examples of Group VI elements include elements of the VIA group, including oxygen (O) and tellurium (Te). Examples of compounds II-VI are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe or HgTe. In general, the elements in II-VI can be combined with different mole fractions.
    [0011] The wires 20 or pyramids 76, 78 may comprise a dopant. By way of example, for compounds III-V, the dopant may be chosen from the group comprising a group II P dopant, for example magnesium (Mg), zinc (Zn), cadmium (Cd ) or mercury (Hg), a group IV P-type dopant, for example carbon (C) or a group IV N-type dopant, for example silicon (Si), germanium (Ge), selenium (Se), sulfur (S), terbium (Tb) or tin (Sn). The height of each wire 20 can be between 250 nia and 50 pin. Each wire 20 may have an elongated semiconductor structure along an axis substantially perpendicular to the face 12. Each wire 20 may have a generally cylindrical shape. The axes of two adjacent yarns may be 0.5 to 10 μm apart and preferably 1.5 to 4 μm in size. For example, the son 20 may be regularly distributed, in particular according to a hexagonal network. The height of each pyramid 76, 78 may be between 100 nia and 25 pin. Each pyramid may have an elongate semiconductor structure along an axis substantially perpendicular to the face 12. The base of each pyramid 76, 78 may have a general shape of oval, circular or polygonal type, in particular triangular, rectangular, square or hexagonal. The centers of two adjacent pyramids can be distant from 0.25 gm to 10 gm and preferably from 1.5 gm to 4-pin. By way of example, the pyramids can be regularly distributed, in particular along a hexagonal network. The shell 28 may comprise a multilayer stack comprising in particular: an active layer covering the upper portion of the associated wire or pyramid 76, 78; B13042 18 - an intermediate layer of conductivity type opposite to the lower portion of the wire 20 covering the active layer; and a bonding layer covering the intermediate layer and covered by the electrode. The active layer is the layer from which the majority of the radiation provided by the LED is emitted. In one example, the active layer may include containment means, such as multiple quantum wells. It consists, for example, of an alternation of GaN and InGaN layers having thicknesses of 3 to 20 nm (for example 6 nm) and 1 to 10 nm (for example 2.5 nm), respectively. The GaN layers may be doped, for example of the N or P type. According to another example, the active layer 15 may comprise a single layer of InGaN, for example with a thickness greater than 10 nm. The intermediate layer, for example doped P-type, may correspond to a semiconductor layer or a stack of semiconductor layers and allows the formation of a PN or PIN junction, the active layer being between the intermediate layer of type P and the N-type upper portion of the wire 20 of the PN or PIN junction. The bonding layer may correspond to a semiconductor layer or to a stack of semiconductor layers 25 and allows the formation of an ohmic contact between the intermediate layer and the electrode 30. By way of example, the bonding layer may be doped very strongly of the type opposite the lower portion of the wire 20 or the pyramid 76, 78, until degenerate the semiconductor layer or layers, for example doped P type at a concentration greater than or equal to 1020 atoms / cm3. The stack of semiconductor layers may comprise an electron-blocking layer formed of a ternary alloy, for example gallium aluminum nitride (AlGaN) or indium aluminum nitride (AlInN). contact B13042 19 with the active layer and the intermediate layer, to ensure a good distribution of the electric carriers in the active layer. The electrode 30 is adapted to polarize the active layer 5 of each wire 20 and let the electromagnetic radiation emitted by the LEDs LED. The material forming the electrode 30 may be a transparent and conductive material such as indium tin oxide (ITO), zinc oxide doped with aluminum or graphene. For example, the electrode layer 30 has a thickness of between 5 nm and 200 rua, preferably between 20 nm and 50 rua. The encapsulation layer 34 is made of at least partially transparent insulating material. The maximum thickness of the encapsulation layer 34 is between 250 nm and 50 μm so that the encapsulation layer 34 completely covers the electrode 30 at the top of the LEDs. Alternatively, a mirror conductive layer, not shown, covering the electrode layer 30 between the wires 20 or between the pyramids 76, 78 but not extending over the wires 20 may be provided. The mirror conductive layer may correspond to a metal layer, for example aluminum, silver, copper or zinc. According to another variant, the optoelectronic device 50 may, in addition, comprise a phosphor layer, not shown, provided on the encapsulation layer 34 or merged with it. One embodiment of a method of manufacturing the optoelectronic device 50 shown in FIG. 3 will be described in connection with FIGS. 8A-8C. FIG. 8A illustrates the structure obtained after carrying out the following steps: (1) Formation on the face 12 of the substrate 10 of the seed layer 16.
    [0012] B13042 The seed layer 16 may be deposited by a chemical vapor deposition (CVD) or organometallic chemical vapor deposition (MOCVD) method, also known as organometallic epitaxy. in vapor phase (or MOVPE, acronym for Metal-Organic Vapor Phase Epitaxy). However, processes such as molecular beam epitaxy (MBE), gas-source MBE (MBBE), organometallic MBE (MOMBE), plasma-assisted MBE (RAMBE), Atomic Layer Epitaxy (ALE), hydride vapor phase epitaxy (HVPE) can be used, or an atomic thin layer deposition process can be used. ALD, acronym for Atomic Layer Deposition). In addition, methods such as evaporation or reactive sputtering may be used. When the seed layer 16 is aluminum nitride, it can be substantially textured and have a preferred polarity. The texturing of the layer 16 can be obtained by an additional treatment carried out after the deposition of the seed layer. This is, for example, annealing under an ammonia (NH 3) stream. (2) Deposition of the insulating layer 52, for example 25 according to a compliant deposit, in particular by CVD; and (3) forming the apertures 54 in the insulating layer 52, a single aperture 54 being shown in Figure aA. It may be an anisotropic etching, for example reactive ion etching (RIE) or inductively coupled plasma etching (ICP). FIG. 8B illustrates the structure obtained after the following step: B13042 21 (4) Formation of seeds in each opening 54, three seeds 80, 82, 84 being represented by way of example in FIG. 8B. The process for forming the seeds 80, 82, 84 may be a process of the type CVD, MOCVD, MBE, GSMBE, PAMBE, ALE, HVPE, ALD. In addition, electrochemical processes may be used, for example, chemical bath deposition (CBD), hydrothermal processes, liquid aerosol pyrolysis or electrodeposition.
    [0013] By way of example, the method of forming seeds may comprise injecting into a reactor a precursor of a group III element and a precursor of a group V element. Examples of precursors of Group III elements are trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMA1). Examples of group V precursors are ammonia (NH3), tertiarybutylphosphine (TBP), arsine (A5H3), or asymmetric dimethylhydrazine (UDMH). According to one embodiment, the temperature in the reactor in step (4) is less than or equal to 1000 ° C, preferably less than or equal to 820 ° C. According to one embodiment, the ratio of the precursor gas stream of the group V element to the precursor gas stream of the group III element, or V / III ratio, in step (4) is greater than or equal to 1000, preferably greater than or equal to 5000. FIG. 8C illustrates the structure obtained after the following step: (5) Growth of a wire 20 in each opening 54. The method of growing the wires 20 can be a CVD, MOCVD, MBE, GSMBE, PAMBE, ALE, HVPE, ALD process. In addition, electrochemical processes may be used, for example, chemical bath deposition (CBD), hydrothermal processes, liquid aerosol pyrolysis or electrodeposition.
    [0014] By way of example, the yarn growth process may comprise injecting into a reactor a precursor of a group III element and a precursor of a group V element.
    [0015] Preferably, the temperature in the reactor during step (4) is lower than the temperature in the reactor during step (5). Preferably, the ratio V / III in step (4) is greater than the ratio V / III in step (5).
    [0016] According to one embodiment, the temperature in the reactor in step (5) is greater than or equal to 950 ° C., preferably greater than or equal to 1000 ° C. According to one embodiment, the ratio V / III in step (5) is less than or equal to 100, preferably less than or equal to 50. According to one embodiment of the invention, in step (4) ) and in a first phase of growth of the son of the compound III-V in step (5), a precursor of a further element is added in excess in addition to the precursors of the compound III-V. The additional element may be silicon (Si) An example of a precursor of silicon is silane (SiH4). The presence of silane among the precursor gases results in the incorporation of silicon into the GaN compound. Thus, a lower portion of the N-type doped wire 20 is obtained. In addition, this results in the formation of a silicon nitride layer, not shown, which covers the periphery of the lower portion of the wire, to the exception of the summit as the lower portion of the wire grows. According to one embodiment of the invention, in a second phase of growth of the III-V compound yarns, the operating conditions of the MOCVD reactor described above are, by way of example, maintained with the exception of the fact that the stream of silane in the reactor is reduced, for example by a factor greater than or equal to 10, or stopped. Even when the silane stream is stopped, the upper portion of the thus-obtained wire may be N-type doped due to diffusion in this active portion of dopants from adjacent passivated portions or due to residual GaN doping.
    [0017] As can be seen in FIG. 8C, the sufficiently high height H of the insulating layer 52 causes only the microfilch, whose axis of growth is substantially parallel to the axis of the opening 54, to grow outside the opening 54.
    [0018] The subsequent steps of the method of manufacturing the optoelectronic device 50 are as follows: (6) Epitaxial formation, for each wire 20, of the layers composing the shell 28. The deposition of the layers composing the shell 28 only occurs on the portion of the wire 20 out of the opening 54 of the insulating layer 52. (7) Formation of the second electrode 30, for example by conformal deposition. (8) Formation of the encapsulation layer 34. When the encapsulation layer 34 is made of silicone, the encapsulation layer 34 can be deposited by a spin coating process by a jet printing process. or by a screen printing process. When the encapsulation layer 34 is an oxide, it can be deposited by CVD. (9) Formation by deposition of the first electrode 8, 25 covering the lower face 11 of the substrate 10. (10) Cutting of the substrate 10 to separate the optoelectronic devices. By way of example, the step (9) described above can be carried out between step (7) and step (8) described previously or between step (6) and step (7) described. previously. One embodiment of a method for manufacturing the optoelectronic device 60, shown in FIG. 4, comprises the steps (1) to (10) described above except that step (1) is replaced by step (1). 11) below: B13042 24 (11) Formation of the nucleation layer 16 according to the step (1) described above and etching of the seed layer 16 to form the seed pads 62. The etching of the seed layer 16 can be carried out by dry etching, for example a reactive ion etching or RIE (English acronym for Reactive Ion Etching) or an induction coupled plasma etching or ICP (inductively coupled plasma) engraving. One embodiment of a method of manufacturing the optoelectronic device 70, shown in FIG. 5, comprises the steps (1) to (10) described above except that step (1) is replaced by step (1). 12) below: (12) Formation of the nucleation pads 62 according to the step (11) described above and protection of the portions of the face 12 of the substrate 10 not covered by the seed pads 62 and, optionally, the lateral flanks of the pads germination 62 to prevent subsequent growth of son on these portions. In one example, this can be done by forming a mask at the top of each seed pad 62 and by an oxidation step which causes the formation of the dielectric regions 72 at the surface of the substrate 10 between the seed pads. and dielectric regions 73 on the lateral flanks of each seed pad 62. In another example, this can be achieved by a step of nitriding the surface of the substrate 10 and seed pads 62 which causes the formation of the dielectric regions. 72 on the surface of the substrate 10 between the seed pads 62. An embodiment of a method of manufacturing the optoelectronic devices 75 or 77, shown respectively in FIG. 6 or 7, comprises the steps (1) to (10). ) described above with the difference that step (5) is replaced by the following step (13): (13) Growth of pyramids 76, 78 since each opening 54. The growth process Pyramids 76, 78 may be a CVD, MOCVD, MBE, GSMBE, PAMBE, ALE, B13042 HVPE, ALD method. In addition, electrochemical processes may be used, for example, the CBD process, hydrothermal processes, liquid aerosol pyrolysis or electrodeposition. Growth conditions are chosen in order to grow the crystalline structures preferably in the form of pyramids and not son. FIG. 9 shows the structure obtained in step (13) during the growth of pyramid 76. The replacement of step (1) by step (11) described above can be applied also for structures pyramidal or truncated pyramids. FIG. 10 is a sectional, partial and schematic view of an embodiment of an optoelectronic device 90 with light-emitting diodes. The optoelectronic device 90 comprises the same elements as the optoelectronic device 50 shown in FIG. 3 with the difference that each opening 54 is replaced by an opening comprising two successive opening portions 92 and 94 having different dimensions. The two opening portions 92, 94 are preferably coaxial. By way of example, the insulating layer 52 is replaced by a stack of two insulating layers 96 and 98. The insulating layer 96 covers the nucleation layer 16 and comprises the openings 92. Each opening 92 exposes a portion of the layer 25 nucleation 16. Each opening 92 has a height H1 and a diameter L1, preferably substantially constant over the entire height H1. The insulating layer 98 covers the insulating layer 96 and includes the apertures 94. Each aperture 94 exposes one of the apertures 92 and a portion of the insulating layer 96 around the aperture 92. Each aperture 94 has a height H2 and an aperture 92. diameter L2, preferably substantially constant over the entire height H2. In the present embodiment, the diameter L1 is strictly smaller than the diameter L2.
    [0019] By way of example, the height H1 of each opening 92, that is to say the thickness of the insulating layer 96, is between 30 nm and 500 nm, preferably between 100 nm and 300 nm. For example, the diameter L1 of each opening 92 is between 30 nia and 1 pin, preferably between 100 nia and 600 nia. The ratio F1 between the height H1 and the diameter L1 is between 0.1 and 4, preferably between 0.75 and 1.5. For example, the height H2 of each opening 94, that is to say the thickness of the insulating layer 98, is between 200 nia and 2000 nia, preferably between 250 nia and 500 nia. By way of example, the diameter L 2 of each opening 94 is between 50 μm and 2 μm, preferably between 150 μm and 800 μm. The ratio F2 between the height H2 and the diameter L2 is between 0.1 and 4, preferably between 0.75 and 1.5.
    [0020] The insulating layers 96, 98 may be composed of the same material or different materials. By way of example, one of the layers 96, 98 is of silicon oxide (SiO 2) and the other layer is of silicon nitride (SixNy, where x is approximately equal to 3 and y is approximately equal to 4, for example Si3N4). Alternatively, the openings 92, 94 are formed in a single insulating layer. Alternatively, the layer 96 is not made with an insulating material but with a semiconductor material, in particular AIN, or metal, especially Ti, TiN, Ta, TaN, Hf, HfN, W, Mo for example with the one of the materials described above for the lower layers of the layer 52. The diameter L1 of the opening 92 is selected to promote the growth of a single seed in the opening 92. The diameter L2 of the opening 94 is selected by according to the desired diameter of the wire 20. An embodiment of a method of manufacturing the optoelectronic device 90 comprises the steps (1) to (10) described above except that the steps (2) and (3) are replaced by the following step (14): B13042 27 (14) Successive deposition of the insulating layers 96 and 98 and formation of the openings 94 and the openings 92. When the materials composing the insulating layers 96 and 98 are different, the openings 94 can be formed da ns the insulating layer 98 by etching which is selective with respect to the material forming the insulating layer 96. When the materials composing the insulating layers 96 and 98 are the same, the depth of the openings 94 can be controlled by the duration of the etching.
    [0021] A variant of this method consists in first depositing the layer 96 and then making each opening 92. After this step, the insulating layer 98 is deposited which may optionally fill the openings 92. The openings 94 are then made using an etching selective to the material forming the insulating layer 98. Figure 11 is a partial sectional and schematic sectional view of an embodiment of an optoelectronic device 100 with light emitting diodes. The optoelectronic device 100 comprises the same elements as the optoelectronic device 50 shown in FIG. 3, with the difference that each opening 54 is replaced by an opening comprising two successive portions 102 and 104 having different dimensions. By way of example, the insulating layer 52 is replaced by a stack of two layers 106 and 108, the layer 106 covering the nucleation layer 16 and comprising the openings 102. The layer 108 is made of an electrically insulating material. Each opening 102 exposes a portion of the nucleation layer 16. Each opening 102 has a height H3 and a diameter L3, preferably substantially constant over the entire height H3. The insulating layer 108 comprises the openings 104, covers the insulating layer 106 and is cantilevered with said insulating layer 106 at each opening 102. Each opening 104 has a height H4 and a diameter L4.
    [0022] In the present embodiment, the diameter L4 is strictly smaller than the diameter L3. By way of example, the height H3 of each opening 102, that is to say the thickness of the insulating layer 106, is between 30 and 500 nia, preferably between 100 and 300 nia. By way of example, the diameter L 3 of each opening 102 is between 100 μm and 2 μm, preferably between 200 μm and 800 μm. The ratio F3 between the height H3 and the diameter L3 is between 0.1 and 5, preferably between 0.4 and 1.5.
    [0023] By way of example, the height H4 of each opening 104, that is to say the thickness of the insulating layer 108, is between 50 nm and 500 nm, preferably between 100 nm and 300 nm. By way of example, the diameter L4 of each opening 104 is between 30 nia and 1 pin, preferably between 100 nia and 400 nia. The ratio F4 between the height H4 and the diameter L4 is between 0.1 and 2, preferably between 0.5 and 2.0. According to one embodiment, the insulating layers 106, 108 are composed of different materials. By way of example, one of the layers 106, 108 is made of silicon oxide (5i02) and the other layer is silicon nitride (SixNy, where x is about 3 and y is about 4 for example Si3N4). According to another embodiment, the layer 106 is made of aluminum nitride and the layer 108 is made of silicon nitride. The diameter L3 of the aperture 102 is selected to make it substantially certain that at least one seed will grow in the aperture 102 on the nucleation layer 16. The diameter L4 of the aperture 94 is selected according to the desired diameter. 20 and is sufficiently narrow to select the yarn from a single seed in the case where several seeds are formed in the opening 102. Advantageously, the dimensions of the opening 102 are a control parameter of the germ formation and the dimensions of the aperture 104 are a control parameter of the selection of a single wire. As a result, the control parameters of seed formation and selection of a single wire do not depend on a single aperture and can be adjusted independently. One embodiment of a method of manufacturing the optoelectronic device 100 shown in FIG. 11 will be described in connection with FIGS. 12A-12C. The embodiment is described in the case where the layers 106 and 108 are insulating layers. Nevertheless, this embodiment can be applied in the case where the layer 106 is not electrically insulating in nature. This embodiment comprises the steps (1) to (10) described above with the difference that the steps (2) and (3) are replaced by the following steps: (15) Successive deposition of the insulating layers 106 and 108 (FIG. 12A). (16) Formation of the aperture 104 by anisotropic etching (FIG. 12B) of the material of the insulating layer 108, this etching being selective or not with respect to the material of the insulating layer 106. In the case where this etching does not is not selective with respect to the material of the insulating layer 106, the etching is completed after a determined time. (17) Formation of the opening 102 by an isotropic etching (FIG. 12C), from the opening 104, of the material of the insulating layer 106, this etching being selective with respect to the material of the insulating layer 108. Examples of isotropic etchings of silicon oxide or silicon nitride are hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), ammonium fluoride (NH4F) or a solution of BOE (Acronym for Buffered Oxide Etch). Examples of anisotropic etchings of silicon oxide or silicon nitride are trifluoromethane (CHF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) or nitrogen trifluoride (NF3). , to which can be added inert or nearly inert carrier gases such as dihydrogen, helium, argon or oxygen, so as to adjust the etch rates.
    [0024] By way of example, H3PO4 can be used to selectively etch silicon oxide with respect to silicon nitride. By way of example, a fluorine-carbon plasma such as C5F8 + O2 + Ar can be used to etch silicon nitride selectively with respect to silicon oxide. Another embodiment of a method of manufacturing the optoelectronic device 100 shown in FIG. 11 will be described in connection with FIGS. 1A and 13B. This embodiment comprises the steps (1) to (10) described above with the difference that the steps (2) and (3) are replaced by the following steps: (18) Successive deposition of the insulating layers 106 and 108. ( 19) Formation of the opening 104 by anisotropic etching of the material of the insulating layer 108 and an opening 109 in the extension of the opening 104 by anisotropic etching of the material of the insulating layer 106 (Figure laA). The etching used is not selective with respect to the materials constituting the insulating layers 106 and 108. This is, for example, an etching of the type CHF3 + O2 or CF4 + H2. (20) Formation of the aperture 102 by isotropic etching (FIG. 13B), from the aperture 109, of the material of the insulating layer 106, this etching being selective with respect to the material of the insulating layer 108. FIG. 14 is a sectional view, partial and schematic, of an embodiment of an optoelectronic device 110 with light emitting diodes. The optoelectronic device 110 comprises the same elements as the optoelectronic device 50 shown in FIG. 3, with the difference that each opening 54 is replaced by an opening 112 having a height H5 having a diameter which increases as a function of the height when away from the substrate 10. L5 is called the smallest diameter of the aperture 112 and L6 is the largest diameter of the aperture 112.
    [0025] By way of example, the height H5 of each opening 112 is between 30 nia and 1 pin, preferably between 200 nia and 600 nia. By way of example, the diameter L5 is between 30 nm and 600 nm, preferably between 100 nm and 400 nm. By way of example, the diameter L6 is between 50 μm and 2 μm, preferably between 350 μm and 800 μm. The ratio F5 between the height H5 and the diameter L5 is between 0.5 and 10, preferably between 0.75 and 4. The diameter L5 at the base of the opening 112 is selected to promote the growth of a seed. unique to the portion of the seed layer 16 exposed by the opening 112. The diameter L6 at the apex of the opening 112 is selected according to the desired diameter of the wire 20. An embodiment of a method of manufacturing the device Optoelectronics 110 of Figure 14 will be described in connection with Figures 15A to 15C. This embodiment comprises the steps (1) to (10) described above with the difference that the steps (2) and (3) are replaced by the following steps: (21) Successive deposition of the insulating layer 52 and a resin layer 114 and etching an opening 116 in the resin layer exposing a portion of the insulating layer 52 (Figure 15A). (22) Formation of the opening 112 by a partially anisotropic etching (FIG. 15B) of the material of the insulating layer 52. By way of example, the etching may be an RIE (acronym for reactive ion etching) type etching. The anisotropic character may be more important at the beginning of the etching than at the end of the etching. (23) Removal of the resin layer 114 (Fig. 15C). As a variant, the layer 114 may be a hard mask, for example made of a dielectric material, for example silicon oxide SiO 2 or silicon nitride SiN. In the previously described embodiments with reference to FIGS. 10 and 11, the formation of the seeds and growth of the yarns is achieved after the openings 92, 94, 102, 104 are formed in the layers 96, 98, 106. 108, however, alternatively, the sprouting step and a portion of the growth of the strands in the openings 92, 102 can be performed before the insulating layer formation step. 108 and the step of forming the openings 94, 104. One embodiment of such a method of manufacturing the optoelectronic device 100 shown in FIG. 8 will be described in connection with FIGS. 16A to 16F. This embodiment comprises the steps (1) to (10) described above with the difference that the steps (2) and (3) are replaced by the following steps: (24) Deposition of the layer 106 on the seed layer 16 (Figure 16A). (25) Formation of apertures 102 in layer 106 (FIG. 16B). (26) Formation of seeds in each aperture 102 and growth of one or more threads in each aperture 102 so as to obtain a semiconductor portion 118 substantially completely filling the aperture 102 (Fig. 16C). (27) Deposition of the insulating layer 108 on the insulating layer 106 and on the semiconductor portions 118 (Figure 16D). (28) Formation of apertures 104 in layer 108 to expose a portion of semiconductor portions 118 (Fig. 16E). (29) Growth of a yarn in each aperture 104 from the semiconductor portion 118 a semiconductor portion 120 being shown in each aperture 104 (Fig. 16F). The embodiments described previously with reference to FIGS. 7, 8 and 11 have been described in the case of a seed layer 16 covering the substrate 10.
    [0026] However, these embodiments can also be implemented by using, in place of the seed layer 16, seed pads 62 as described in connection with FIG. 4 or using insulating blocks. 71, possibly formed of a stack of two insulating blocks as has been described with reference to FIG. 5. The embodiments described above in connection with FIGS. 10, 11 and 14 have been described in the case of a growth. subsequent semiconductor elements of the microfil or nanowire type. These embodiments may also be applied in the case of growth of pyramid or truncated pyramid type semiconductor elements. In the embodiments described above, the shell 28 covers each wire 20 up to the insulating layer 52, 98 or 108. However, as an alternative, an insulating layer may be provided which covers a portion of the lateral flanks of the insulation. each wire 20 on part of the height of the wires 20 outside the openings 54, 94, 104, 112. The shell 28 then covers the lateral flanks of the son 20 except at the locations where this insulating layer is present. This insulating layer may further cover a portion of the shell 28. Particular embodiments of the present invention have been described. Although embodiments have been described for an optoelectronic device for which the shell 28 covers the top of the associated wire 20 and a portion of the sidewalls of the wire 20, the shell may be provided only at the top of the wire 20 .
    权利要求:
    Claims (18)
    [0001]
    REVENDICATIONS1. Optoelectronic device (50; 60; 70; 75; 77; 90; 100; 110) comprising semiconductor elements (20; 76; 78), each semiconductor element resting on a support (16; 62) through an opening ( 54, 92, 94, 102, 104, 112) formed in a portion (52; 71; 96, 98; 106, 108) at least partially covering the support and at least a first portion of which is insulating, the height (H) of the opening being greater than or equal to 100 nia and less than or equal to 3000 nia and the ratio between the height (H) and the smallest diameter of the opening (L; L2; L4; L5) being greater than or equal to 0.5 and less than or equal to 10.
    [0002]
    Optoelectronic device according to claim 1, wherein the semiconductor elements (20; 76; 78) are nanowires, microwires and / or pyramidal structures of nanometric or micron size.
    [0003]
    Optoelectronic device according to claim 1 or 2, wherein the height (H) is greater than or equal to 200 nia.
    [0004]
    An optoelectronic device according to any one of claims 1 to 3, wherein the ratio is greater than or equal to 1.
    [0005]
    An optoelectronic device according to any one of claims 1 to 4, wherein the average diameter (L) of the aperture (54) is constant over the entire height of the portion (52; 71).
    [0006]
    An optoelectronic device according to any one of claims 1 to 4, wherein the average diameter of the aperture (112) decreases continuously from the apex of the aperture to the base of the aperture. 30
    [0007]
    An optoelectronic device according to any one of claims 1 to 4, wherein the aperture comprises successively from the base of the aperture a first portion (92; 102) and a second portion (94; 104), the average diameter the first portion being constant over the entire height of the first portion and the average diameter of the second portion being constant over the entire height of the second portion and different from the average diameter on the first portion.
    [0008]
    Optoelectronic device according to claim 57, wherein the average diameter (L1) of the first portion (92) is strictly less than the average diameter (L2) of the second portion (94).
    [0009]
    An optoelectronic device according to claim 7, wherein the average diameter (L3) of the first portion (102) is strictly greater than the average diameter (L4) of the second portion (104).
    [0010]
    An optoelectronic device according to any one of claims 1 to 9, wherein the first portion of the portion (96, 98; 106, 108) comprises at least one of silicon oxide materials, silicon and aluminum oxides.
    [0011]
    An optoelectronic device according to any one of claims 1 to 10, wherein at least a second portion of the portion (96, 98; 106, 108) comprises at least one non-electrically insulating material.
    [0012]
    An optoelectronic device according to any one of claims 1 to 9, wherein the second portion of the portion (96, 98; 106, 108) comprises at least one of the materials selected from the group consisting of AIN, Ti, TiN , Ta, TaN, Hf, HfN, W WN, Mo.
    [0013]
    An optoelectronic device according to any one of claims 1 to 12, wherein each semiconductor element (20; 76,77) is predominantly a compound 30
    [0014]
    An optoelectronic device according to claim 13, wherein each semiconductor element (20; 76,78) comprises predominantly gallium nitride.
    [0015]
    15. A method of manufacturing an optoelectronic device comprising the following steps: forming, on a support (16; 62), a portion (52; 71; 96, 98; 106, 108) at least partially covering the support and at least a first part of which is insulating; forming an opening (54; 92,94; 102,104; 112) extending through the portion, the height (H) of the opening being greater than or equal to 100 nia and less than or equal to 3,000 nia and the ratio of height to the average diameter of the opening at the top of the portion being greater than or equal to 0.5 and less than or equal to 10; and growing in each aperture a semiconductor element (20; 76,77) supported on the support.
    [0016]
    The method of claim 15, wherein the height (H) of the portion (52; 71; 96,98; 106,108) is greater than or equal to 100 nia and less than or equal to 1000 nia.
    [0017]
    The method of claim 16, wherein forming the portion (52; 71; 96,98; 106,108) comprises the steps of: depositing a first insulating layer (106) comprising a first insulating material; depositing a second insulating layer (108) comprising a second insulating material different from the first insulating material; forming a first portion (104) of the opening in the first insulating layer; forming a second portion (102) of the opening in the second portion of the insulating layer, the average diameter of the first portion being different from the average diameter of the second portion; and growing in each first and second portion of the aperture a semiconductor element (20) supported on the support.
    [0018]
    The method of claim 16, wherein forming the portion (52; 71; 96,98; 106,108) comprises the steps of: depositing a first insulating layer (96) comprising a first insulating material; forming a first portion (92) of the opening in the first insulating layer; depositing a second insulating layer (98) comprising a second insulating material different from the first insulating material; forming a second portion (94) of the opening in the second portion of the insulating layer, the average diameter of the first portion being different from the average diameter of the second portion; and growing in each first and second portion of the aperture a semiconductor element (20) resting on the support.
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    同族专利:
    公开号 | 公开日
    FR3016082B1|2017-05-05|
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    EP3090450B1|2020-02-19|
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    WO2015101578A1|2015-07-09|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1363700A|FR3016082B1|2013-12-30|2013-12-30|OPTOELECTRONIC DEVICE WITH SEMICONDUCTOR ELEMENTS AND METHOD OF MANUFACTURING THE SAME|FR1363700A| FR3016082B1|2013-12-30|2013-12-30|OPTOELECTRONIC DEVICE WITH SEMICONDUCTOR ELEMENTS AND METHOD OF MANUFACTURING THE SAME|
    US15/108,738| US10153399B2|2013-12-30|2014-12-23|Optoelectronic device comprising semiconductor elements and its fabrication process|
    EP14820890.3A| EP3090450B1|2013-12-30|2014-12-23|Optoelectronic device comprising semiconductor elements and its fabrication process|
    PCT/EP2014/079276| WO2015101578A1|2013-12-30|2014-12-23|Optoelectronic device comprising semiconductor elements and its fabrication process|
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